This invention relates to logic circuits, and in particular to a static, ratioed type logic circuit suitable for use with an input logic network having a large self-loading capacitance.
Field-effect transistors are commonly used in logic circuits, and as is well known, the metal-oxide-semi-conductor field-effect transistor, hereinafter referred to simply as a "MOSFET", is preferred for many logic circuit applications due primarily to the MOSFET's essentially two dimensional structure which lends itself to high volume fabrication using integrated circuit techniques. The MOSFETS described herein are all assumed to be P-channel, enhancement-mode devices generally of the type described in U.S. Pat. Nos. 3,618,050 and 3,631,465 issued to R. H. Heeren, Nov. 2, 1971 and Dec. 28, 1971, respectively. However, other types of transistors may, of course, be substituted in a straightforward manner if appropriate changes in the biasing are made where necessary.
In one conventional circuit, shown in FIG. 1, a load device, MOSFET Q.sub.11, functioning as a resistor, applies a dc supply voltage -V.sub.DD from supply point 13 to output node 12. A logic network 15, is shown as a single MOSFET Q.sub.13, but may be any arrangement of series transistors, parallel transistors, or a combination of series and parallel transistors. Network 15 connects output node 12 to a fixed potential reference point 11 (normally ground) and for a given set of input signals applied to the logic network via input lead 14, a conductive path is provided between output node 12 and reference point 11. This grounds the output node, causing the output voltage to go to substantially zero. For all other sets of input signals, an open circuit exists between node 12 and reference point 11, and the output voltage is a negative voltage, -V. This output is applied to any appropriate load, but it is most conveniently used to charge a capacitive load C.sub.L.
This circuit is a static circuit and is termed ratioed since the control of the output voltage at output node 12 is dependent upon the ratio of the impedance between the load device and the logic network. The resistance of the load device Q.sub.11 must be many times higher than the resistance of network 15 if node 12 is to be pulled substantially to the potential of reference point 11.
A problem arises where logic network 15 contains a large self-loading capacitance, shown in phantom as C.sub.SL ; this condition exists, for example, where the network is a switch assembly with a large associated wiring capacitance or a large memory structure of, for example, an integrated array of thousands of transistors with its inherent associated capacitances. When the logic network produces a conductive path between reference point 11 and output node 12, the output voltage is established substantially at the reference or ground potential of point 11, and the self-loading capacitance is of no consequence. However, when the logic network creates an open circuit between reference point 11 and output node 12, the load capacitor is essentially connected in parallel with the self-loading capacitance of the logic network, and the two capacitors are therefore charged together. The combined capacitive effect, especially if the self-loading capacitance is large relative to the load capacitor, creates a very long charging time constant and hence a very slow output response time, as shown in FIG. 1A at 19. It is noted that in this figure and in all discussion hereinafter negative logic is assumed; 0 volts corresponds to a logical 0 and a large negative voltage corresponds to a logical 1. Accordingly, a transition from a negative voltage to zero volts at the input 14 of network 15 (corresponding to a change from logical 1 to logical 0) causes a non-conductive path between node 12 and point 11 to be established. This causes C.sub.L to be charged, but as seen at 19, where a large C.sub.SL is in parallel with C.sub.L, the charging takes place very slowly.
The static ratioed arrangement is, however, not the only type of logic circuit. An alternative configuration, which is inherently faster, utilizes multiphase clock signals to control the circuit operation, rather than relying upon the fixed impedance ratio and changes in the input. This clocking results in a dynamic circuit. As in the static circuits, a logic network creates the open or closed path between a reference point and a common output node in accordance with input data, but clock signals provide the circuit biases instead of dc supplies. Since the circuit operates in response to clocking, the impedance ratio is irrelevant to the operation and these circuits are therefore termed ratioless in distinction to the static ratioed circuits discussed hereinbefore.
There are two possible forms of the basic dynamic logic circuit. Both include an additional gating device connected in series between the logic network and the output node. One arrangement is shown in FIG. 2 and is disclosed in detail in A. S. Farber et. al. U.S. Pat. No. 3,461,312, issued Aug. 12, 1969.
In this circuit MOSFET Q.sub.21 acts as a load device, and MOSFET Q.sub.23 and capacitance C.sub.SL represent a logic network 25, in a manner similar to the circuit of FIG. 1. A gating MOSFET Q.sub.22 has been added in series between logic network 25 and output node 12 and the clocking signals 0.sub.1 and 0.sub.2 are applied to the gates of MOSFETS Q.sub.21 and Q.sub.22 respectively. Reference point 11 and the supply point 13 are again supplied with fixed potential de voltages, -V.sub.DD and ground, respectively. The 0.sub.1 and 0.sub.2 clock pulses are provided at mutually exclusive times as shown in FIG. 2A. During the 0.sub.1 negative interval, the load capacitance C.sub.L is charged regardless of the input since the input is isolated from output node 12, by virtue of Q.sub.22 being OFF. Therefore, if the logic network has a self-loading capacitance C.sub.SL, shown in phantom, it would not be charged, but when gating device Q.sub.22 is turned ON during the 0.sub.2 negative interval, the self-loading capacitance C.sub.SL would share the charge with the capacitive load C.sub.L, hence reducing the output voltage. Thus the self-loading capacitance will, if large compared to the capacitive load, essentially dissipate the output voltage as shown at 29 in FIG. 2A. As this is, of course, unacceptable, this prior art dynamic circuit is totally unsuitable for use with input networks having a large self-loading capacitance.
Another dynamic arrangement is shown in FIG. 3 and described in detail, in an article entitled "Multiphase Clocking Achieves 100-Nsec MOS Memory" by Lee Boysel and Joe Murphy in Electrical Design News June 10, 1968, page 50.
Referring to FIG. 3, Q.sub.31 is a load device and Q.sub.33 and self-loading capacitance C.sub.SL represent a logic network 35. The supply voltage at point 13 and the reference potential at point 11 are provided by the 0.sub.1 clock, shown in FIG. 3A. During the 0.sub.1 pulse interval load capacitor C.sub.L is charged notwithstanding the input signals since there is no ground path in the system. When the 0.sub.1 clock pulse is over, the ground is provided, but due to the 0.sub.2 clock pulse, gating device Q.sub.32 remains ON. Therefore if the input causes a conductive path from the now grounded reference point 11 to output node 12 through Q.sub.32, load capacitor C.sub.L will discharge and the output will go to zero. If the input condition produces an open circuit between point 11 and node 12, the charged condition remains and the output stays at the negative output voltage shown as -V in FIG. 3A. Subsequently Q.sub.32 turns OFF and isolates the input from the output.
The clocking presents numerous constraints upon the circuit design since, of course, the clock signals must be generated and synchronized, and for many applications, the greater simplicity of the static circuit is preferred. Furthermore, this arrangement is not free from the effects of a large self-loading capacitance. If input network 35 contains a large self-loading capacitance C.sub.SL, shown in phantom, when the charging takes place during the 0.sub.1 clock pulse interval, the 0.sub.2 clock is also ON and Q.sub.32 therefore provides a path to C.sub.SL causing both C.sub.L and C.sub.SL to charge together as in the static circuit of FIG. 1. This is shown at 39 in FIG. 3A. The result is, of course, a slow charging response time.
In addition, this circuit causes the load capacitor C.sub.L to charge during each 0.sub.1 pulse interval even if the input conditions corresponds to a zero output, such as at 38, for example. The circuit driven by the output must then also be clocked to sample the output at a time, such as t.sub.s, after the 0.sub.2 pulse.
It is therefore, an object of the present invention to provide a faster operating static logic circuit.
It is a further object to provide a logic circuit which is well suited for operation with a logic network having a large self-loading capacitance.
It is a still further object to provide a logic circuit of the ratioed type which is only superficially affected by the self-loading capacitance of the logic network.
It is a still further object to provide a logic circuit suitable for use with complex logic networks formed by integrated circuit techniques, especially integrated logic networks having small semiconductor areas.